Silicon Nitride Deposition, Chromium Corrosion Mechanisms and Source/Drain Parasitic Resistance in Amorphous Silicon Thin Film transistors

Hydrogenated amorphous silicon (a-Si:H) based thin film transistors (TFTs) are finding increased application as switching elements in active-matrix liquid crystal displays (AMLCDs). Extensive research has been focussed on optimizing fabrication conditions to improve materials quality and on reducing channel length to increase device speed. However, the basic physics and chemistry have not yet been fully understood. In addition, little attention has been paid to the significant effect of source/drain parasitics. The work described in this thesis is closely related to the speed and stability issues on the discrete device level. Specifically, the influence of gate nitride deposition and its NH3 plasma treatment has been studied. The competing effects of nitridation reaction and radiation damage were found to cause an interesting trade-off between the device stability and speed. Further effort was devoted to the analysis of an important TFT failure phenomenon. Both electrical and spectroscopic techniques were utilized for gate Cr corrosion studies. It was determined that the corrosion was largely promoted by the CF4 plasma exposure of Cr during the fabrication. Finally, new test structures were designed, fabricated and characterized to study the source/drain parasitic resistance

Study of a New Silicon Epitaxy Technique: Confined Lateral Selective Epitaxial Growth

This work describes a significant new advance in the technique of silicon selective epitaxy called Confined Lateral Selective Epitaxial Growth (CLSEG). CLSEG is a method for forming thin films of single crystal silicon on top of an insulating layer or film. Such thin films are generically termed Silicon-On- Insulator (SOI), and1 allow dielectric isolation of integrated circuit elements, making them more efficient (faster with lower power), more resistant to radiation, and smaller than conventional integrated circuits, ionizing radiation than conventional integrated circuits. CLSEG offers advantages over current methods of achieving SOI by being easily manufactured, inherently reproducible, and having greater design flexibility. CLSEG is also adaptable to vertical stacking of devices in a circuit, in what is called three-dimensional integration, for even greater reductions in area. In addition, CLSEG can be used for a wide variety of sensor and micromachining application. This thesis describes the design and development of CLSEG, and compares it to the current state of the art in the fields of SOI and Selective Epitaxial Growth (SEG). CLSEG is accomplished by growing silicon selective epitaxy within a cavity; which is formed of dielectric materials upon a silicon substrate. The resulting SOI film can be made as thin as 0.1 micron, and tens of microns wide, with an unlimited length. In particular, there is now strong evidence that surface diffusivity of silicon adatoms on the dielectric masking layers is a significant contributor to the transport of silicon to the growth surface during SE G. CLSEG silicon material quality is evaluated by fabricating a variety of semiconductor devices in CLSEG films. These devices demonstrate the applicability of CLSEG to integrated circuits, and provide a basis of comparison between CLSEG-grown silicon and device-quality substrate silicon. Then, CLSEG is used to fabricate an advanced device structure, verifying the value and significance of this new epitaxy technique. In the final two chapters, CLSEG is evaluated as a technology, and compared to the current state of the art. Then, a method is presented Tor forming CLSEG with only one photolithography step, and a process is described for making a SOI film across an entire silicon wafer using CLSEG. These techniques may indicate the feasibility of using CLSEG for three dimensional integration of microelectronics. It is hoped that this work will establish a firm basis for further study of this interesting and valuable new technology

MODELING OF GROWTH RATES OF SELECTIVE EPITAXIAL GROWTH (SEG) AND EPITAXIAL LATERAL OVERGROWTH (ELO) OF SILICON IN THE SIH2CL2-HCL-H2 SYSTEM

A semi-empirical model for the growth rate of selective epitaxial silicon(SEG) in the Dichlorosilane-HC1-Hz system that represents the experimenltal data has been presented. All epitaxy runs were done using a Gemini-I LPCVD pancake reactor. Dichlorosilane was used as the source gas and hydrogen as the carrier gas. Hydrogen Cllloride(HC1) was used to ensure that no nucleation took place on the oxide. The growth rate expression was considered to be the sum of a growth term dependent on the partial pressures of Dichlorosilane and hydrogen, and an etch berm that varies as the partial pressure of HC1. The growth and etch terms were found to have an Arrhenius relation with temperature, with activation energies of 52kcal/mol and 36kcal/mol respectively. Good agreement was obtained with experimental data. The variation of the selectivity threshold was correctly predicted, which had been a problem with earlier models for SEG growth rates. SEG/ELO Silicon was grown from 920-970°C at 40 and 150 torr pressures for a variety of HCI concentrations. In addition previous data collected by our research group at 820-1020°C and 40-150torr were used in the model

SELF-ALIGNED SINGLE CRYSTAL CONTACTED HIGH-SPEED SILICON BIPOLAR TRANSISTOR UTILIZING SELECTIVE (SEG) AND CONFINED SELECTIVE EPITAXIAL GROWTH (CLSEG)

A new high-speed bipolar transistor structure, the ELOBJT-3, is proposed as a novel application of selective epitaxy technology. The new structure is greatly suited to high-speed ECL circuits, where Ccb, C,, and Rbx are of prime importance. The reduction of these parasitics to their nearly theoretical minimums is accomplished through the use of dielectric isolation and concentric contacting. For extremely high speed operation, dimensions can be scaled to sub-micron size due to the completely self-aligned emitter-base region. Simulation was used to compare important device parameters of the ELOBJT-3 device and a comparably sized existing high speed bipolar structure. Results showed significant improvement in all three of the investigated parameters. Rbx, Ccb, and C, had reductions of 77, 58, and 43 percent respectively. These simulated values were used in a circuit simulation where ELOBJT-3 devices provided a 37% reduction of propagation delay. The device simulations verified the ELOBJT-3\u27s significantly reduced parasitics and propensity for high speed operation. The ELOBJT-3 self-aligned pedestal structure was obtained following considerable process development. It was found that CLSEG could be grown within- an oxide cavity without the use of nitride. If nitride was used, a passivation technique was developed which virtually eliminated nucleation and clogging at the via holes. A PNP configured ELOBJT-3 device with N+ doped CLSEG base contacts was built to establish feasibility of the self-aligned structure. Also, fully functional NPN devices were built in a simplified structure with current gains up to 90. Dislocations and defects at the SEG edge produced unacceptable emitter-collector leakage currents unless the emitter was moved away from the SEG edge. The reported problems with junctions located at SEG sidewalls were avoided by moving the junction out of the sidewall area. Finally, parasitic measurements were correlated with computer simulation to validate the previous comparison simulations

CHARACTERIZATION OF DUAL-GATED FULLY-DEPLETED SO1 MOSFETS THAT UTILIZE SILICON SELECTIVE EPITAXIAL GROWTH

Fully-depleted single-gated and dual-gated SOI MOSFETs are fabricated using both Epitaxial Lateral Overgrowth (ELO) and Confined Lateral Selective Epitaxial Growth (CLSEG). SOI MOSFETs and diodes are fabricated in thin (= 1500A) CLSEG films grown in pre-defined 2500A, thick cavities for the first time. In addition to the SOI MOSFETs fabricated using selective epitaxial growth, thin-film SO1 MOSFETs were also fabricated on SIMOX wafers. The one to one comparison between the two SOI technologies proves that the EL0 and CLSEG material is of at least as good if not better quality than that of SIMOX. Effective hole mobilities in the excess of 300 cm2/V-sec were obtained on thin-film EL0 and pp,eff values of greater than 240 cm2/V-sec were extracted from the thin-film CLSEG devices. A new linear sweep technique to measure generation lifetimes in thin SOI films has been developed. The measurement technique uses fully-depleted or partially depleted MOSFETs as the test structure. A detailed analytical formulation that involves the solution of Poisson\u27s equation as applied to a fully-depleted SOI structure is presented. The analytical solutions are used to simulate the behavior of the SOI devices under the proposed linear sweep conditions. Finally, the linear sweep technique is applied to fullydepleted devices fabricated on SIMOX material and an average lifetime of 2μs is extracted from devices across the waCer. The effects of volume inversion in thin-film short-channel SO1 MOSFETs and the efficacy of dual-gate operation in enhancing their device performance have been analyzed using two dimensional device simulations and one-dimensional analytical computations. In the strong inversion regime, the analyses suggest that when compared at constant VG VT values, the dual-channel volume inverted devices do not offer significant currentenhancement advantges, other than that expected from the second channel, over the conventional single-channel devices for silicon film thicknesses in the 0.1μm range. In its support however, two-dimensional simulations suggest that dual-gated devices are more immune to short channel effects than conventional single-gated devices. In this regard, a novel process sequence to fabricate self-aligned dual-gated MOSFETs is presented

A NITRIDED-OXIDE DIELECTRIC FOR EPITAXIAL LATERAL OVERGROWTH APPLICATIONS

Polyoxide gate dielectric degradation problems were encountered during the process development of a three-dimensional CMOS structure. In prior studies, the gate dielectric degradation was found to occur when the polyoxide was exposed to the oxygen deficient, low pressure silicon rich epitaxial lateral overgrowth (ELO) ambient . The durability of thin polyoxide dielectrics is essential to three-dimensional process, allowing bottom gate control of the vertically stacked PMOS load device. The previous process had approximately a 1000 A minimum thickness limit on the bottom gate dielectric, unacceptable when compared to modern day CMOS technology. This research was directed at developing a durable high quality 100-300 A nitrided polyoxide (NPOX) gate dielectric process. The incorporation and distribution of nitrogen in both ammonia nitrided polyoxide (NPOX) and nitrided silicon dioxide (NOX) dielectric films were studied. The effects of the nitrogen concentration and distribution on the resistance of the NPOX and NOX films to EL0 ambient degradation were tletermined. It was observed that the surface nitrogen concentration had no effect on the durability of the dielectric. However, a bulk nitrogen concentration as low as 8 at% significantly reduced the formation of EL0 ambient induced pinholes in 250A dielectric films. After 40 min. of EL0 stress the electrical yield was raised from 0%, for polyoxide and silicon dioxide dielectric capacitors, to over 80% for NPOX and NOX dielectric capacitors. Analyses of the failed devices suggest that active pinhole generation still existed, however, the bulk nitrogen concentration dramatically reduced the frequency and speed at which these defects were produced. Fixed oxide charges and interface state densities on the order of 1 .2*101 1 were observed after 1100 C, 10 min. nitridation with NPOX capacitor yields of\u27 84% after 40 min. of EL0 growth ambient stressing. After 60 minutes of nitridation, the surface became resistant to the EL0 growth ambient induced surface pitting and roughening

Low Temperature Silicon Selective Epitaxial Growth(SEG) and Phosphorous Doping in a Reduced-Pressure Pancake Reactor

Pancake reactors operated at low temperatures and reduced-pressures have been used for silicon selective epitaxial growth (SEG). In general, dichlorosilane (DCS) is the silicon source gas, hydrogen is the carrier gas, and HCl prevents the formation of polysilicon on the silicon dioxide. An investigation of growth rate, uniformity, and doping characteristics of SEG silicon grown at reduced pressures between 40 and 150 Torr and temperatures between 820°C and 1020°C in a pancake reactor is presented. The dependences of growth rates and uniformities on growth temperatures, pressures, and doping were studied. Improvement in thickness uniformity across the wafer was achieved by lowering the deposition temperature and pressure. In-situ phosphorus doping in the range of 1016-1018P atoms/cm3 was accomplished by introducing phosphine (PH3) gas into the reactor during epitaxial deposition. Doping concentration, which was determined by three different methods, increased with phosphine inject set point. Also, higher phosphorus concentrations were obtained at lower deposition temperatures and/or pressures. Diodes and bipolar transistors identically fabricated in undoped SEG and in bulk silicon were used to characterize the SEG material quality. Since average ideality factors, leakage currents, breakdown voltages, and current gains extracted from 970°C-40T SEG devices were similar to those of substrate devices, the material quality of the SEG deposited at 970°C and 40 torr was indicated to be as good as the bulk silicon

MICROMECHANICAL SENSORS USING MERGED EPITAXIAL LATERAL OVERGROWTH OF SILICON

A novel technology for manufacturing thin silicon diaphragm structures is presented. Controllability of thin silicon diaphragm is one of the most important issues in fabricating silicon micromechanical sensors whose sensitivity depends on the diaphragm thickness. This can be accomplished by epitaxial lateral overgrowth (ELO) of single crystal silicon on a patterned layer of masking material, typically Si02, combined with crystallographic etching of which etching rate depends on the crystal plane. With recent improvement of EL0 material, good quality of lOμm thick, 200μm x lOOOμm single crystal silicon was obtained with its thickness being precisely controlled by growth rate (≤ lμ m/min.). The junction leakage of the p-n junction diodes fabricated on merged EL0 silicon indicated the material quality is comparable to the substrate silicon. Using this technology, a bridge-type piezoresistive accelerometer with four beams and one proof mass was fabricated successfully. Its sensitivity and resonant frequency were comparable to the accelerometers made by other methods. They were analyzed by comparing the experimental results to a simple analytical solution as well as ANSYS stress simulator using a finite element: methods. The experimental results showed a potential application of the new technology to silicon sensor fabrication but some further refinement is remaining. Free-standing single crystal cantilever beams were fabricated using, MELO and RIE, of over lOOOμm long and 5μm by 10μm in cross section. These beams were very short, straight, indicating little residual stress. Wide, short beams were fabricated using EL0 which were also free standing. Special treatment of MELO indicated that diodes and bipolar transistors fabricated on top of the oxide stripes showed nearly ideal characteristics, hence the quality of the MELO was improved. With MELO of thicker than 5μm, no voids were observed. Test structures significantly with all surface micromachining, were designed for further development of silicon membranes

Electronic Circuit Analysis and Design

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